Since the invention of integrated circuits by Dr. Jack Kilby of Texas Instruments in early years, scientists and engineers have made numerous inventions and improvements in semiconductor devices and processes. In the past 50 years, the size of semiconductors has been significantly reduced, which leads to increasing processing speed and decreasing power consumption. To date, the development of semiconductors has largely followed Moore's Law, which roughly states that the number of transistors in dense integrated circuits doubles roughly every two years. Now, the semiconductor processes are being developed toward 20 nm or less, and some of the companies are embarking on the 14 nm process. Here, by way of providing only one reference, a silicon atom is about 0.2 nm, which means that the distance between two separate components manufactured by means of a 20 nm process is only about one hundred silicon atoms.
The manufacturing of semiconductor devices has therefore become increasingly challenging and advancing toward the physically possible limit. One of the recent developments in semiconductor technology has been the use of silicon germanium (SiGe) in semiconductor manufacturing. With the evolution of integrated circuit developments, functional densities (e.g., the number of interconnection line elements per chip area) are also generally increasing while the geometrical dimensions (i.e., the smallest element or line that can be produced using a process) are reduced. This size reduction process can often provide benefits in terms of increasing production efficiency and reducing associated costs; however, with the continuous development of integrated circuit manufacturing technology, MOS transistors are getting smaller and smaller in characteristic size. In order to reduce the parasitic capacitance at the gate of an MOS transistor, the speed of the device is increased and the gate stack structure of a high-K gate dielectric layer and a metal gate is introduced into the MOS transistor. In order to avoid the influence of the metal material of the metal gate on the other structures of the transistor, the gate stack structure of the metal gate and the high-K gate dielectric layer is usually fabricated by means of a “gate last” process.
The appearance of the metal gate can make the size of the MOSFET (Metallic Oxide Semiconductor Field Effect Transistor) very small, but correspondingly, while gradually reducing the volume of the MOSFET, in the process of forming the metal gate in the prior art, the metal is not easily deposited into a trench, voids are easily created, resulting in the performance degradation of the device.
Therefore, there is an urgent need for a semiconductor manufacturing method, which can well deposit a metal gate electrode, so that the interior of the prepared metal gate is less likely to form voids, so as to ensure the reliability of the metal gate and the good device performance of the semiconductor.